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SA303 SA303u p r o d u c t i n n o v a t i o n f r o m description the SA303 is a fully integrated switching amplifer designed primarily to drive three-phase brushless dc (bldc) motors. three independent half bridges provide over 10 amperes peak output current under microcontroller or dsc control. thermal and short cir - cuit monitoring is provided, which generates fault sig - nals for the microcontroller to take appropriate action. a block diagram is provided in figure 1. additionally, cycle-by-cycle current limit offers user programmable hardware protection independent of the microcontroller. output current is measured using an innovative low loss technique. the SA303 is built using a multi-technology process allowing cmos logic con - trol and complementary dmos output power devices on the same ic. use of p-channel high side fets en - ables 60v operation without bootstrap or charge pump circuitry. the power quad surface mount package balances ex - cellent thermal performance with the advantages of a low profle surface mount package. features ? low cost 3 phase intelligent switching amplifer ? directly connects to most embedded micro - controllers and digital signal controllers ? integrated gate driver logic with dead-time generation and shoot-through prevention ? wide power supply range (8.5v to 60v) ? over 10a peak output current per phase ? 3a continuous output current per phase ? independent current sensing for each output ? user programmable cycle-by-cycle current limit protection ? over-current and over-temperature warning signals applications ? 3 phase brushless dc motors ? multiple dc brush motors ? 3 independent solenoid actuators 3 phase switching amplifier SA303 p r o d u c t i n n o v a t i o n f r o m figure . block diagram copyright ? cirrus logic, inc. 2009 (all rights reserved) http://www.cirrus.com m ay 2009 apex ? SA303ureva s a 3 0 3 s w i t c h i n g a m p l i f i e r v s ( p h a s e a ) p g n d ( a & b ) g a t e c o n t r o l p w m s i g n a l s a b c o u t a o u t b o u t c p g n d ( c ) t e m p gnd v s ( p h a s e b & c ) v s + i lim / d i s 1 s c d i s 2 s g n d p h a s e a p h a s e c p h a s e b c o n t r o l l o g i c v dd i a ' i b ' i c ' i a ' i b ' i c ' f a u l t l o g i c i a i c i b a t a b b t b b c t c b v dd v dd v dd
SA303 2 SA303u p r o d u c t i n n o v a t i o n f r o m . ch aracteristics and s pecifications absolute maximum r atings parameter symbol min max units supply voltage v s 60 v supply voltage v dd 5.5 v logic input voltage (-0.5) (v dd +0.5) v output current, peak, 10ms (note 2) i out 10 a power dissipation, avg, 25oc (note 2) p d 100 w temperature, solder, 10sec t s 260 c temperature, junction (note 2) t j 150 c temperature range, storage t stg ?55 125 c operating temperature, case t a ?40 125 c parameter test conditions (note 1) min typ max units logic input low 1 v input high 1.8 v output low 0.3 v output high 3.7 v output current (sc, temp, i lim /dis1) 50 ma power supply v s uvlo 50 60 v v s undervoltage lockout, (uvlo) 8.3 v v dd 4.5 5.5 v supply current, v s 20 khz (one phase switching at 50% duty cycle) , v s =50v, v dd =5v 25 30 ma supply current, v dd 20 khz (one phase switching at 50% duty cycle) , v s =50v, v dd =5v 5 6 ma current limit current limit t hreshold (v th ) 3.75 v v th hysteresis 100 mv output current, continuous 25oc case temperature 3 a rising delay , td(rise) see figure 10 270 ns f alling delay , td( fall) see figure 10 270 ns disable dela y, td(dis) see figure 10 200 ns enable delay , td( dis ) see figure 11 200 ns rise time, t(rise) see figure 11 50 ns f all t ime, t( fall) 50 ns on resistance sourcing (p-channel) 3a load 400 m? on resistance sinking (n-channel) 3a load 400 m? s pecifications
SA303 SA303u 3 p r o d u c t i n n o v a t i o n f r o m notes: * the specifcation of SA303a is identical to the specifcation for SA303 in applicable column to the left. 1. (all min/max characteristics and specifcations are guaranteed over the specifed operating condi - tions. typical performance characteristics and specifcations are derived from measurements taken at typical supply voltages and t c = 25c). 2. long term operation at elevated temperature will result in reduced product life. de-rate internal power dissipation to achieve high mtbf. 3. output current rating may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do not exceed the specifed current rating or a junction temperature of 150c. parameter test conditions (note 1) min typ max units thermal thermal w arning 135 oc thermal w arning hysteresis 40 oc/w resistance, junction to case full temperature range 1.25 1.5 oc/w temperature range, case meets specifcations -40 85 oc figure 2. 64-pin qfp, p ackage style hq s pecifications, continued
SA303 4 SA303u p r o d u c t i n n o v a t i o n f r o m diode forward voltage - top fet (p-channel) 0 1 2 3 4 5 forward voltage (v) current (a) 0.5 1.5 1.3 1.1 0.9 0.7 diode forward voltage - bottom fet (n-channel) 0 1 2 3 4 5 forward voltage (v) current (a) 0.5 1.5 1.3 1.1 0.9 0.7 on resistance - top fet 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 i out ,(a) rds(on),(?) v s =11 v s =13 v s =15 v s >17 10 0 9 8 7 6 5 4 3 2 1 (p-channel) on resistance - bottom fet 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 10 i out ,(a) rds(on),(?) v s =11 v s =13 v s =15 v s =17 v s >22 0 9 8 7 6 5 4 3 2 1 (n-channel) power derating 0 20 40 60 80 100 120 case temperature, t c power dissipation, p d -40 120 80 40 0 v dd supply current 4.5 4.6 4.7 4.8 4.9 5 0 50 100 150 200 250 300 frequency ( khz ) v dd supply current (ma) one phase switching @ 50% duty cycle; v s =50v v dd supply current 4 4.5 5 5.5 6 6.5 7 7.5 8 10 20 30 40 50 60 v s supply voltage (v) v dd supply current ( m a) one phase switching frequency = 20 khz 50% duty cycle 25c 125c current sense 0.1 1 10 0.01 0.1 1 10 sense current ( m a) load current (a) v s supply current 20 40 60 80 100 120 140 160 180 0 50 100 150 200 250 300 frequency ( khz ) v s supply current (ma) one phase switching @ 50% duty cycle; v s =50v 0 v s supply current 0 5 10 15 20 25 v s supply voltage (v) v s supply current ( m a) 125c 25c one phase switching frequency = 20 khz 50% duty cycle 10 20 30 40 50 60
SA303 SA303u p r o d u c t i n n o v a t i o n f r o m figure 3. ex ternal connections t able . pin descriptions 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 out c out c nc v s b & c v s b & c v s b & c v s b & c nc out b out b out b nc pgnd a & b pgnd a & b pgnd a & b pgnd a & b nc out a out a out a ic nc sc nc ib nc i lim /dis1 nc sgnd nc bt nc bb nc ab nc at nc v dd nc out c nc pgnd c pgnd c pgnd c hs hs nc cb nc ct nc nc v s a v s a v s a nc hs hs temp nc dis2 nc ia pin # pin name signal type simplifed pin description 29,30,31 v s (phase a) power high voltage supply (8.5-60v) supplies phase a only 51,52,53 out c power output half bridge c power output 55,56,57 pgnd (phase c) power high current gnd return path for power output c 3 sc logic output indication of a short of an output to supply, gnd or another phase 61 cb logic input logic high commands c phase lower fet to turn on 63 ct logic input logic high commands c phase upper fet to turn on 1 ic analog output phase c current sense output 5 ib analog output phase b current sense output 7 i lim /dis1 logic input/output as an output, logic high indicates cycle-by-cycle current limit, and logic low indicates normal operation. as an input, logic high places all outputs in a high impedance state and logic low disables the cycle-by-cycle current limit function.
SA303 6 SA303u p r o d u c t i n n o v a t i o n f r o m pin # pin name signal type simplifed pin description 9 sgnd power analog and digital gnd C internally connected to pgnd 11 bt logic input logic high commands b phase upper fet to turn on 13 bb logic input logic high commands b phase lower fet to turn on 15 ab logic input logic high commands a phase lower fet to turn on 17 at logic input logic high commands a phase upper fet to turn on 19 v dd power logic supply (5v) 21 ia analog output phase a current sense output 23 dis2 logic input logic high places all outputs in a high impedance state 25 temp logic output thermal indication of die temperature above 135oc 42,43,44 out b power output half bridge b power output 46,47,48,49 v s (phase b&c) power high voltage supply phase b&c 33,34,35 out a power output half b ridge a power output 37,38,39,40 pgnd (phase a& b) power high current gnd return path for power outputs a& b 26,27,58,59 hs mechanical pins connected to the package heat slug 2,4,6,8,10, 12,14,16,18, 20,22,24,28, 32,36,41,45, 50,54,60,62, 64 nc --- do not connect .2 pin descriptions v s : supply voltage for the output transistors. these pins require decoupling (1f capacitor with good high frequen - cy characteristics is recommended) to the pgnd pins. the decoupling capacitor should be located as close to the v s and pgnd pins as possible. additional capacitance will be required at the v s pins to handle load cur - rent peaks and potential motor regeneration. refer to the applications section of this datasheet for additional discussion regarding bypass capacitor selection. note that v s pins 29-31 carry only the phase a supply current. pins 46-49 carry supply current for phases b & c. phase a may be operated at a different supply voltage from phases b & c. both v s voltages are monitored for undervoltage conditions. out a, out b, out c: these pins are the power output connections to the load. note: when driving an induc - tive load, it is recommended that two schottky diodes with good switching characteristics (fast t rr specs) be connected to each pin so that they are in parallel with the parasitic back-body diodes of the output fets. (see section 2.6) pgnd: power ground. this is the ground return connection for the output fets. return current from the load fows through these pins. pgnd is internally connected to sgnd through a resistance of a few ohms. see section 2.1 of this datasheet for more details. sc: short circuit output. if a condition is detected on any output which is not in accordance with the input com - mands, this indicates a short circuit condition and the sc pin goes high. the sc signal is blanked for approxi - mately 200ns during switching transitions but in high current applications, short glitches may appear on the sc pin. a high state on the sc output will not automatically disable the device. the sc pin includes an internal 12k series resistor. ab, bb, cb: these schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower n-channel output fets on and off. logic high turns the bottom n-channel fet on, and a logic low turns the low side n-channel fet off. if ab, b b, or cb is high at the same time that a corresponding at, b t, or ct input is high, protection circuitry will turn off both fets in order to prevent shoot-through on that output phase. protection circuitry also includes a dead-time generator, which inserts dead time in the outputs in the case of simultane - ous switching of the top and bottom input signals. t able . pin descriptions - c ont.
SA303 SA303u p r o d u c t i n n o v a t i o n f r o m at, bt, ct: these schmitt triggered logic level inputs are responsible for turning the associated top side, or upper p-channel fet outputs on and off. logic high turns the top p-channel fet on, and a logic low turns the top p-channel fet off. ia, ib, ic: current sense pins. the SA303 supplies a positive current to these pins which is proportional to the cur - rent fowing through the top side p-channel fet for that phase. commutating currents fowing through the backbody diode of the p-channel fet or through external schottky diodes are not registered on the current sense pins. nor do currents fowing through the low side n-channel fet, in either direction, register at the cur - rent sense pins. a resistor connected from a current sense pin to sgnd creates a voltage signal representa - tion of the phase current that can be monitored with adc inputs of a processor or external circuitry. the current sense pins are also internally compared with the current limit threshold voltage reference, vth. if the voltage on any current sense pin exceeds vth, the cycle by cycle current limit circuit engages. details of this functionality are described in the applications section of this datasheet. i lim /dis: this pin is directly connected to the disable circuitry of the SA303. pulling this pin to logic high places out a, out b, and out c in a high impedance state. this pin is also connected internally to the output of the current limit latch through a 12k resistor and can be monitored to observe the function of the cycle-by-cycle current limit feature. pulling this pin to a logic low effectively disables the cycle-by-cycle current limit feature. sgnd: this is the ground return connection for the v dd logic power supply pin. all internal analog and logic circuitry is referenced to this pin. pgnd is internally connected to gnd through a resistance of a few ohms,. however, it is highly recommended to connect the gnd pin to the pgnd pins externally as close to the device as possible. failure do to this may result in oscillations on the output pins during rising or falling edges. vdd: this is the connection for the 5v power supply, and provides power for the logic and analog circuitry in the SA303. this pin requires decoupling (at least 0.1f capacitor with good high frequency characteristics is rec - ommended) to the sgnd pin. dis2: the dis2 pin is a schmitt triggered logic level input that places out a, out b , and out c in a high imped - ance state when pulled high. dis2 has an internal 12k pull-down resistor and may therefore be left uncon - nected. temp: this logic level output goes high when the die temperature of the SA303 reaches approximately 135oc. this pin will not automatically disable the device. the temp pin includes a 12k series resistor. hs: these pins are internally connected to the thermal slug on the reverse of the package. they should be con - nected to gnd. neither the heat slug nor these pins should be used to carry high current. nc: these no-connect pins should be left unconnected. 2. SA303 operation the SA303 is designed primarily to drive three phase motors. however, it can be used for any application requir - ing three high current outputs. the signal set of the SA303 is designed specifcally to interface with a dsp or microcontroller. a typical system block diagram is shown in the fgure below. over-temperature, short-circuit and current limit fault signals provide important feedback to the system controller which can safely disable the output drivers in the presence of a fault condition. high side current monitors for all three phases provide performance information which can be used to regulate or limit torque.
SA303 SA303u p r o d u c t i n n o v a t i o n f r o m figure 4. system diagram SA303 switching amplifier brushless motor vs (phase a) pgnd (a&b) current monitor signals sensor ? hall sensors or sensorless ? input from stator leads a b c out a out b out c pgnd (c) gnd vs (phase b&c) vs + sensing circuits gnd sgnd g a t e c o n t r o l c o n t r o l l o g i c f a u l t l o g i c t e m p i lim / d i s 1 s c i a i c i b v dd p w m s i g n a l s d i s 2 s g n d a t a b b t b b c t c b m i c r o c o n t r o l l e r or dsc
SA303 SA303u 9 p r o d u c t i n n o v a t i o n f r o m sgnd gate control vs out a pgnd at ab sc temp sc logic temp sense ref ia dis2 i lim /dis1 uvlo ia' + _ lim b lim c + _ vdd lim a current sense 12k 12k 12k 12k vth the block diagram in figure 5 illustrates the features of the input and output structures of the SA303. for simplicity, a single phase is shown. figure . i nput and output structures for a single phase at, bt, ct ab, bb, cb ia, ib, ic i lim / dis 1 d is 2 out a, out b, out c comments 0 0 x x x high-z top and bottom output fets for that phase are turned off. 0 1 v th 1 x high-z voltage on ia, ib, or ic has exceeded vth, which causes i lim /dis 1 to go high. this internally disables top and bottom output fets for all phases. x x x x 1 high-z dis 2 pin pulled high, which disables all outputs. x x x pulled high x high-z pulling the i lim /dis 1 pin high externally acts as a second disable input, which disables all output fets. x x x pulled low 0 determined by pwm inputs pulling the dis 2 pin low externally disables the cycle-by-cycle current limit function. the state of the outputs is strictly a function of the pwm inputs. x x x x x high-z if v s is below the uvlo threshold all output fets will be disabled. table 2. truth t able
SA303 0 SA303u p r o d u c t i n n o v a t i o n f r o m 2. layout considerations output traces carry signals with very high dv/dt and di/dt. proper routing and adequate power supply bypassing ensures normal operation. poor routing and bypassing can cause erratic and low effciency operation as well as ringing at the outputs. the v s supply should be bypassed with a surface mount ceramic capacitor mounted as close as possible to the vs pins. total inductance of the routing from the capacitor to the v s and gnd pins must be kept to a minimum to pre - vent noise from contaminating the logic control signals. a low esr capacitor of at least 25f per ampere of output current should be placed near the SA303 as well. capacitor types rated for switching applications are the only types that should be considered. note that phases b & c share a v s connection and the bypass recommendation should refect the sum of b & c phase current. the bypassing requirements of the v dd supply are less stringent, but still necessary. a 0.1f to 0.47f surface mount ceramic capacitor (x7r or npo) connected directly to the v dd pin is suffcient. sgnd and pgnd pins are connected internally. however, these pins must be connected externally in such a way that there is no motor current fowing in the logic and signal ground traces as parasitic resistances in the small signal routing can develop suffcient voltage drops to erroneously trigger input transitions. alternatively, a ground plane may be separated into power and logic sections connected by a pair of back to back schottky diodes. this isolates noise between signal and power ground traces and prevents high currents from passing between the plane sections. unused area on the top and bottom pc b planes should be flled with solid or hatched copper to minimize inductive coupling between signals. the copper fll may be left unconnected, although a ground plane is recommended. 2.2 fault indications in the case of either an over-temperature or short circuit fault, the SA303 will take no action to disable the outputs. instead, the sc and temp signals are provided to an external controller, where a determination can be made re - garding the appropriate course of action. in most cases, the sc pin would be connected to a fault input on the processor, which would immediately disable its pwm outputs. the temp fault does not require such an immediate response, and would typically be connected to a gpio, or keyboard interrupt pin of the processor. in this case, the processor would recognize the condition as an external interrupt, which could be processed in software via an interrupt service routine. the processor could optionally bring all inputs low, or assert a high level to either of the disable inputs on the SA303. figure 6 shows an external sr fip-fop which pro - vides a hard wired shutdown of all outputs in re - sponse to a fault indication. an sc or temp fault sets the latch, pulling the disable pin high. the processor clears the latched condition with a gpio. this circuit can be used in safety critical applications to remove software from the fault-shutdown loop, or simply to reduce processor overhead. in applications which may not have available gpio, the temp pin may be externally connected to the adjacent dis1 pin. if the device temperature reaches ~135oc all outputs will be disabled, de-energizing the motor. the SA303 will re-energize the motor when the device temperature falls below approximately 95oc. the temp pin hysteresis is wide to reduce the likelihood of thermal oscillations which can greatly reduce the life of the device. 2.3 under-voltage lockout the undervoltage lockout condition results in the SA303 unilaterally disabling all output fets until v s is above the uvlo threshold indicated in the spec table. there is no external signal indicating that an undervoltage lock figure 6. ex ternal f ault l atch circuit s a 303 p r o c e ss o r i n t e rr up t g p i o p w m s c d i s 2 t e m p l a t c h e d f a u l t f a u l t r ese t
SA303 SA303u p r o d u c t i n n o v a t i o n f r o m out condition is in progress. the SA303 has two vs connections: one for phase a, and another for phases b & c. the supply voltages on these pins need not be the same, but the uvlo will engage if either is below the threshold. hysteresis on the uvlo circuit prevents oscillations with typical power supply variations. 2.4 current sense external power shunt resistors are not required with the SA303. forward current in each top, pchannel output fet is measured and mirrored to the respective current sense output pin, ia, ib and ic. by connecting a resistor between each cur - rent sense pin and a reference, such as ground, a voltage develops across the resistor that is pro - portional to the output current for that phase. an adc can monitor the voltages on these resistors for protection or for closed loop torque control in some application confgurations. the current sense pins source current from the vdd supply. headroom required for the current sense circuit is approximately .5v. the nominal scale factor for each proportional output current is shown in the typical performance plot on page 4 of this datasheet. 2. cycle-by-cycle current limit in applications where the current in the motor is not directly controlled, both the average current rating of the mo - tor and the inrush current must be considered when selecting a proper amplifer. for example, a 1a continuous motor might require a drive amplifer that can deliver well over 10a peak in order to survive the inrush condition at startup. because the output current of each upper output fet is measured, the SA303 is able to provide a very robust cur - rent limit scheme. this enables the SA303 to safely and easily drive virtually any brushless motor through a startup inrush condition. with limited current, the starting torque and acceleration are also limited. the plot in figure 7 shows starting current and back emf with and without current limit enabled. if the voltage of any of the three current sense pins exceeds the current limit threshold voltage (vth), all outputs are disabled. after all current sense pins fall below the vth threshold voltage and the offending phases top side input goes low, the output stage will return to an active state on the rising edge of any top side input command signal (at, b t, or ct). with most commutation schemes, the current limit will reset each pwm cycle. this scheme regulates the peak current in each phase during each pwm cycle as illustrated in the timing diagram below. the ratio of average to peak current depends on the inductance of the motor winding, the back emf developed in the motor, and the width of the pulse. figure 8 illustrates the current limit trigger and reset sequence. current limit engages and i lim /dis1 goes high when any current sense pin exceeds vth. notice that the moment at which the current sense signal exceeds the vth threshold is asynchronous with respect to the input pwm signal. the difference between the pwm period and the motor winding l/r time constant will often result in an audible beat frequency sometimes called a sub-cycle oscil - lation. this oscillation can be seen on the i lim /dis1 pin waveform in figure 8. input signals commanding 0% or 100% duty cycle may be incompatible with the current limit feature due to the absence of rising edges of at, bt, and ct except when commutating phases. at high rpm, this may result in poor performance. at low rpm, the motor may stall if the current limit trips and the motor current reaches zero without a commutation edge which will typically reset the current limit latch. t i m e non-l i m i t e d b a c k emf li m i t e d b a ck e m f li m i t e d m o t o r c ur r ent non-l i m i t e d m o t or c u rre n t figure 7. s tart -up v oltage and current
SA303 2 SA303u p r o d u c t i n n o v a t i o n f r o m the current limit feature may be disabled by tying the i lim /dis1 pin to gnd. the current sense pins will continue to provide top fet output current information. typically, the current sense pins source current into grounded resistors which pro - vide voltages to the current limit compara - tors. if instead the current limit resistors are connected to a voltage output dac, the current limit can be controlled dynami - cally from the system controller. this tech - nique essentially reduces the current limit threshold voltage to (vth-vdac). during expected conditions of high torque de - mand, such as start-up or reversal, the dac can adjust the current limit dynami - cally to allow periods of high current. in normal operation when low current is ex - pected, the dac output voltage can in - crease, reducing the current limit setting to provide more conservative fault protec - tion. 2.6 external flyback diodes external fy-back diodes will offer superior reverse recovery character - istics and lower forward voltage drop than the internal back-body di - odes. in high current applications, external fyback diodes can reduce power dissipation and heating during commutation of the motor current. reverse recovery time and capacitance are the most important param - eters to consider when selecting these diodes. ultra-fast rectifers offer better reverse recovery time and schottky diodes typically have low capacitance. individual application requirements will be the guide when determining the need for these diodes and for selecting the component which is most suitable. a t input outa ia v th i lim /dis1 figure 8. current limit w avefor ms figure 9. sch ottky diodes outa outc outb v s v s v s SA303
SA303 SA303u 3 p r o d u c t i n n o v a t i o n f r o m figure 0. timing diagrams 3. power dissipation the thermally enhanced package of the SA303 al - lows several options for managing the power dissi - pated in the three output stages. power dissipation in traditional pwm applications is a combination of output power dissipation and switching losses. output power dissipation depends on the quadrant of operation and whether external fyback diodes are used to carry the reverse or commutating cur - rents. switching losses are dependent on the fre - quency of the pwm cycle as described in the typi - cal performance graphs. the size and orientation of the heatsink must be selected to manage the average power dissipation of the SA303. applications vary widely and various thermal techniques are available to match the re - quired performance. the patent pending mounting technique shown in figure 12, with the SA303 in - verted and suspended through a cutout in the pcb is adequate for power dissipation up to 17w with the hs33, a 1.5 inch long aluminum extrusion with four fns. in free air, mounting the pc b perpendicular to the ground, such that the heated air fows upward along the channels of the fns can provide a total ja of less than 14 oc/w (9w max average p d ). mounting the pcb parallel to the ground impedes the fow of heated air and provides a ja of 16.66 oc/w (7.5w max average p d ). in applications in which higher power dissipation is expected or lower junction or case temperatures are required, a larger heatsink or circulated air can signifcantly improve the performance. 4. ordering and product status inform ation model temperature package production status SA303-ihz -25 to 85oc 64 pin power qfp (hq package drawing) samples available 1q09 top input bottom input delay timing output disable td(fall) td(dis) td(rise) td(dis) td(dis) td(dis) top input bottom input output t(fall) t(rise) 20% 80% fig ure . output response
SA303 4 SA303u p r o d u c t i n n o v a t i o n f r o m figure 2. heatsink technique p atent pending c ontacting cirrus logic support for all apex precision power product questions and inquiries, call toll free 800-546-2739 in north america. for inquiries via email, please contact tucson.support@cirrus.com. international customers can also request support by contacting their local cirrus logic sales representative. to fnd the one nearest to you, go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnifcation, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives con - sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop - erty or environmental damage (critical applications). cirrus products are not designed, authorized or warranted to be suitab le for use in products surgically implanted into the b ody, automotive safety or security devices, life support prod - ucts or other critical applications. inclusion of cirrus products in such applications is understood to b e fully at the cus - tomers risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantab ility and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customers customer uses or permits the use of cirrus products in critical applications, customer agrees, b y such use, to fully indemnify cirrus, its officers, directors, employees, distrib utors and other agents from any and all liability, including attorneys fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs, apex and apex precision power are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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